A lightweight circuit editor to visualize, rearrange and simulate digital netlists.

Features

• rich and lightweight interface with DPI scaling, with a Blender like UX
• netlists import / export, verilog export
• auto routing of series-parallel netlists
• nmos, pmos, pullup and pulldown components to represent NMOS, PMOS and CMOS circuits
• switch level simulation, signal analyzer
• lua scripting for advanced simulations (shipped with an Intel 4004 demo)
• hierarchical circuits with groups
• linked group instances
• layers and images reference
• command line interface
• unit tests

Webapp

If you don’t want to run a third party binary on your computer, you can try this webassembly version instead.
Note that the webapp is slower than the native version. You can force DPI scaling to 100% by adding ?dpi=1.0 to the URL.

• 2026-09-09 Version 0.4.0 LTS (beta)
  • Built in logic components with accurate transistor representation (CMOS, NMOS)
  • DZI support
  • Autosave

Downloads

• 2023 version
• 2026-08-31 Version 0.3.0
  • Debian Bookworm build
  • Windows build (64-bit)

Documentation and examples

Work in progress

Coming soon

• standard cells matching from a reference cell library

Disclaimer

This is a personal tool I developed on my free time for my own needs.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE AND NONINFRINGEMENT. 

IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

YOU ASSUME TOTAL RESPONSIBILITY AND RISK FOR YOUR USE OF THE SOFTWARE.